We have IP core such as JPEG CODEC IP and high-speed interface IP (MIPI standard) that is based on a technology such as the image processing that we cultivated through SoC&ASIC development.
JPEG IP core complies with various JPEG format and our IP has achieved high-speed, small-scale and power-thrifty processing by installing our original algorithms.
MIPI IP core complies with MIPI standerd which works on FPGA. It makes possible to use MIPI interface circuit using FPGA without developing ASIC.
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